1. Field of the Invention
The present invention relates to phase-locked loops, and in particular to a phase-locked loop made in an integrated circuit.
2. Discussion of the Related Art
FIG. 1 schematically shows a phase-locked loop conventionally used in frequency synthesis. The phase-locked loop includes a voltage-controlled oscillator (VCO) 2 generating a periodic output signal of frequency Fout to be synchronized on a reference frequency Fref. A comparison circuit 4 compares a signal with reference frequency Fref and with a frequency signal Fdiv equal to a division of frequency Fout by a predetermined factor N. Comparison circuit 4 provides a control signal to an integrator low-pass filter 6. Filter 6 provides a voltage Vcom for controlling oscillator 2. Frequency Fout varies between minimum and maximum frequencies, in an operating range characteristic of the oscillator, when voltage Vcom varies between minimum and maximum values.
The phase-locked loop is made in an integrated circuit, except for filter 6, as will be seen hereafter. The characteristics of the integrated components may vary along with the manufacturing process. In particular, the operating range of oscillator 2 may vary along with the manufacturing process, which may cause a malfunction of the phase-locked loop. To solve this problem, the operating range of oscillator 2 is adjustable by an adjustment signal FA, generated by a control and adjustment circuit 8. Circuit 8 is provided to control whether the oscillator is in a desired operating range or not. For this purpose, circuit 8 ensures that voltage Vcom of oscillator 2 does not have a value greater than a high threshold value VH, or that it does not have a value smaller than a low threshold value VL. If voltage Vcom is greater than value VH, circuit 8 generates an adjustment signal FA adapted to adjusting the operating range of oscillator 2 upwards. If Vcom is smaller than value VL, circuit 8 generates an adjustment signal FA adapted to adjusting the operating range of oscillator 2 downwards. The taking into account of the value of voltage Vcom by circuit 8 is periodically activated by a clock signal CKaj. Signal CKaj is generated by a frequency divider 9 based on reference frequency Fref.
FIG. 2 schematically shows an implementation of oscillator 2 and adjustment and control circuit 8. Oscillator 2 includes a negative-resistance amplifier 10, the output of which is the oscillator output. The input of amplifier 10 is connected to a first terminal of a capacitor C. The second terminal of capacitor C is connected to the oscillator input via a resistor R. The cathode of a varicap diode Dv is connected to the second terminal of capacitor C. The anode of diode Dv is connected to a ground GND. An inductance L and a variable capacitor Cv are connected in parallel between the input of amplifier 10 and the ground. The capacitance of variable capacitor Cv is controlled by signal FA. As an example (not shown), adjustment signal FA may be a digital signal and capacitor Cv may be formed of a capacitor of predetermined value connectable in parallel with several capacitors by switches, each controlled by one bit of adjustment signal FA. Oscillator 2 has the following operating frequency:Fout=½π[L(Cv+Cdv)]1/2, 
where Cdv is the dynamic capacitance of varicap diode Dv, which varies according to control voltage Vcom. The adjusting of the capacitance of capacitor Cv by adjustment signal FA enables adjusting the oscillator operating range. Control and adjustment circuit 8 includes comparators 12 and 14 enabling comparing voltage Vcom with values VH and VL. Comparators 12 and 14 control a coding block 16. Coding block 16 controls via an adder the incrementation or the decrementation of adjustment signal FA, stored in a D flip-flop 18 clocked by clock signal CKaj. The value of voltage Vcom is thus taken into account by circuit 8 at each rising edge of signal CKaj, and causes, if necessary, an immediate adjustment of the operating range.
FIG. 3 illustrates the variations of frequency Fout of the oscillator according to voltage Vcom for different values of adjustment signal FA. For simplicity, the capacitance of variable capacitor Cv is assumed to only be able to take two values, and digital adjustment signal FA is assumed to only take values 0 or 1. In practice, adjustment signal FA may be comprised of several bits and the capacitance of capacitor Cv may take a great number of values. Voltage Vcom varies between a minimum value Vmin and a maximum value Vmax. In the illustrated example, the capacitance of capacitor Cv is maximum when adjustment signal FA is 0. The oscillator then is in a low frequency range. Frequency Fout then linearly varies between a low frequency FL0 when voltage Vcom has a value Vmin and a high frequency FH0 when voltage Vcom has a value Vmax. When adjustment signal FA is 1, the oscillator is in a high frequency range. Frequency Fout then linearly varies between a low frequency FL1 when voltage Vcom has a value Vmin, and a high frequency FH1 when voltage Vcom has a value Vmax. Threshold values VH and VL, which define the voltage range out of which circuit 8 controls an adjustment of the oscillator operating range, are respectively chosen to be slightly smaller than value Vmax and slightly greater than value Vmin. For simplicity, it is considered hereafter that values Vmin and Vmax are substantially equal respectively to ground GND and to value Vdd of the circuit supply voltage.
When the value of voltage Vcom is taken into account by circuit 8, if adjustment signal FA is 0 and if voltage Vcom has a value greater than VH, circuit 8 brings adjustment signal FA from 0 to 1. Similarly, if adjustment signal FA is 1 and if the value of voltage Vcom is smaller than value VL, circuit 8 brings adjustment signal FA from 1 to 0. The operating ranges of the oscillator partially overlap, and oscillator 2 and control and adjustment circuit 8 are chosen so that the median frequency of the upper range substantially corresponds to the high frequency of the lower range. Similarly, the median frequency of the lower range substantially corresponds to the low frequency of the upper range.
FIG. 4 illustrates the variation of frequency Fout of the oscillator according to control voltage Vcom and the variation of voltage Vcom along time in the previously-described phase-locked loop.
It is assumed that, initially, the phase-locked loop is stabilized at a frequency F1 belonging to the lower operating range of the oscillator. Voltage Vcom then has a value V1.
At a time t0, the equilibrium of the phase-locked loop is modified to control a change in output frequency Fout from frequency F1 to a higher frequency F2. The equilibrium of the phase-locked loop is for example modified by increasing the division ratio N determining variable frequency Fdiv. Comparison circuit 4 detects a difference between reference frequency Fref and variable frequency Fdiv, and controls an increase of voltage Vcom. Voltage Vcom is brought from its value V1 to a value V2 corresponding to frequency F2 in the lower operating range of the oscillator. Voltage Vcom varies from value V1 to value V2 in a damped sinusoid. It is assumed, in the illustrated example, that value V2 is greater than threshold value VH.
At a time t1, the value of voltage Vcom is taken into account by control and adjustment circuit 8. Vcom being greater than VH, circuit 8 determines that the oscillator no longer is in the desired operating range, and it brings the oscillator into its upper operating range. Voltage Vcom still is at value V2, and the oscillator then oscillates at a frequency F3 close to maximum frequency FH1 of the oscillator in the upper operating range. The oscillator frequency is then greater than the desired frequency F2. The phase-locked loop then tends to reduce the oscillator frequency. To achieve this, the phase-locked loop brings voltage Vcom from value V2 to a desired value V4, corresponding to frequency F2 in the upper operating range of the oscillator, in a damped sinusoid (shown in dotted lines). Voltage Vcom varies from value V2 to the desired value V4 in a convergence duration Δt, taking intermediary values which may be located out of voltage range VL-VH, although the desired value V4 is in this voltage range. If control and adjustment circuit 8 took into account the value of voltage Vcom at a time when this voltage is outside of range VL-VH, it would, wrongly, determine that the oscillator is in a poorly adapted frequency range. Convergence duration Δt depends on values V2 and V4 and on the characteristics of the phase-locked loop. Conventionally, to avoid for circuit 8 to take into account the intermediary values of voltage Vcom, the period with which the value of voltage Vcom is taken into account is chosen to be greater than the maximum convergence duration Δt of voltage Vcom. In some cases, however, in particular for some embodiments of comparison circuit 4 and of filter 6 of FIG. 1, the convergence duration Δt during which voltage Vcom is likely to take intermediary values located outside voltage range VL-VH may be particularly lengthened.
FIG. 5 illustrates an example of embodiment of a comparison circuit 4 and of an integrator low-pass filter 6 likely to lengthen convergence duration Δt.
Comparison circuit 4 includes a phase/frequency comparator 20 comprised of two D flip-flops respectively clocked at frequencies Fref and Fdiv, having their input terminals connected to a logic level 1. The output terminals of the D flip-flops respectively generate signals UP and DWN. The D flip-flops are reset by a NAND combination of signals UP and DWN. An output terminal A of comparison circuit 4 is connected via a switch 22 to a source 24 of a positive constant current +I. Switch 22 is respectively on or off when signal UP is at 1 or 0. Output terminal A is also connected via a switch 26 to a source 28 of a negative constant current −I. Switch 26 is respectively on or off when signal DWN is equal to 1 or to 0.
Filter 6 includes a capacitor C1 of high value connected in series with a resistor R1 between terminal A and the ground. A capacitor C2 of low value as compared to C1 is also connected between terminal A and the ground. Capacitor C1 plays the function of an integrator of the current provided by circuit 4. Capacitor C2 eliminates the high-frequency components of the current provided by circuit 4.
When a small difference exists between frequencies Fref and Fdiv, comparison circuit 4 provides short current pulses to filter 6. If the current pulses are positive, capacitors C1 and C2 charge at constant current during each pulse. Capacitor C1 charges through resistor R1, while capacitor C2 charges through a negligible parasitic resistance. Between two consecutive pulses, capacitor C2 discharges into capacitor C1 through resistor R1. Similarly, if the current pulses are negative, capacitors C1 and C2 discharge at constant current during each pulse and capacitor C2 charges from capacitor C1 through resistor R1 between two consecutive pulses. The mean value of control voltage Vcom then depends on the difference between reference frequency Fref and variable frequency Fdiv provided by the oscillator, and the phase-locked loop operates normally.
However, when frequencies Fref and Fdiv are very different, comparison circuit 4 provides long current pulses to filter 6. At the beginning of a long current pulse, capacitors C1 and C2 charge (respectively, discharge) at constant current. Capacitor C2 charges (respectively, discharges) rapidly. From the time when capacitor C2 is charged (respectively, discharged), to the end of the current pulse, voltage Vcom is maintained at value Vdd (respectively, GND). Considering that no current is absorbed by oscillator 2, all the current provided by comparison circuit 4 then flows through resistor R1. The voltage drop in resistor R1, of high value, then is on the order of Vdd and capacitor C1 is charged (respectively, discharged) with a reduced current. Further, the duration separating the consecutive current pulses may be too short for capacitor C2 to have time to completely discharge (respectively, to completely charge) into capacitor C1 between two consecutive current pulses. Voltage Vcom is then maintained at a value close to Vdd (respectively, to GND).
FIG. 4 illustrates (in full line) the variation of frequency Fout according to voltage Vcom and the variation of voltage Vcom along time in a phase-locked loop comprised of comparison circuit 4 and of filter 6 of FIG. 5. Until time t1, voltage Vcom varies as previously described. It is assumed that at time t1, the difference between frequencies F3 and F2 is sufficiently large for voltage Vcom to be rapidly brought to a value close to ground GND and smaller than value VL. The oscillator then oscillates at a frequency close to minimum frequency FL1 of the upper operating range. The saturation of comparison filter 4 and of filter 6 is such that voltage Vcom keeps a value close to GND until a time t2 when the value of voltage Vcom is taken into account by circuit 8.
At time t2, circuit 8 erroneously determines that the oscillator no longer is in the desired operating range and it brings the oscillator into its lower operating range. Voltage Vcom still is grounded and the oscillator then oscillates at a frequency close to minimum frequency FL0 of the lower operating range. This frequency being much lower than frequency F2, voltage Vcom is rapidly brought to a value close to value Vdd and greater than value VH. Comparison circuit 4 and filter 6 are saturated in such a way that voltage Vcom is maintained at value Vdd until a time t3 at which voltage Vcom is taken into account again by circuit 8.
At time t3, circuit 8 brings the oscillator back into its upper operating range. The phase locked-loop behaves from time t3 as from time t1, and it cannot stabilize.
As seen previously, a solution to prevent such an oscillation of the phase-locked loop is to decrease the frequency with which the value of voltage Vcom is taken into account by control and adjustment circuit 8. The value of voltage Vcom is then always taken into account after the phase-locked loop is stabilized. However, such a solution reduces the frequency with which the oscillator frequency range can be adjusted, even when comparison circuit 4 and filter 6 are not saturated, which is not desirable.